Why Chiplets Are Changing Processor Design

For decades, a processor was one piece of silicon: every core, every cache, every memory controller etched onto a single monolithic die. AMD broke that model in 2019 with its Zen 2 architecture, splitting a CPU into several small dies connected by a high-speed interconnect called Infinity Fabric. The reason is blunt economics: as transistors shrink, a single large die becomes far more likely to contain a fatal manufacturing defect than several small dies stitched together, and that single fact is now reshaping how AMD, Intel, Apple, and Nvidia design nearly every high-performance chip they ship.

This is not a cosmetic packaging trend. It is a direct response to a physical limit in how silicon wafers are manufactured, and understanding it explains why "processor size" no longer means what it did ten years ago.

The yield problem chiplets solve

Chip fabrication is a probability game played out on a thin, circular slice of crystalline silicon called a wafer, typically 300 millimeters across. Photolithography machines etch billions of transistors onto that wafer in layers, and every square millimeter of exposed silicon carries some chance of containing a defect from stray dust, a lithography misalignment, or a material impurity in the substrate. A single flaw in the wrong spot can render an entire die non-functional.

That defect probability compounds with area, and it does not compound in a simple linear way. A widely used way to estimate this is Murphy's yield model, a formula developed for integrated circuit manufacturing that expresses yield as a function of die area and defect density: yield falls off faster than area grows, because a larger die simply has more square millimeters where a single point defect can ruin the whole part. Foundry engineering literature commonly illustrates this with concrete numbers: a die around 510 mm² manufactured on a leading-edge process node with a defect density near 0.09 defects per square centimeter can see estimated yields drop to roughly 60%, while a much smaller die on the identical process, with the identical defect density, clears 90% or higher (Leachman, University of California Berkeley yield modeling notes).

This is why "yield," the percentage of dies on a wafer that work correctly and can be sold, is treated as one of the most important cost variables in the entire chip industry. A large monolithic 700-800 mm² processor manufactured near the reticle limit (the largest area a lithography tool can expose in a single pass, generally capped around 858 mm²) is disproportionately expensive to produce well, because every failed die on that wafer wastes an outsized share of the wafer's total value. A small 70-90 mm² chiplet fabricated on the same process line yields at a much higher rate, and even when a defect does strike, the wasted silicon is a fraction of the cost.

AMD's EPYC server processors and Ryzen desktop chips exploit this directly. Instead of etching one giant die containing every core, memory controller, and I/O block, AMD builds separate small dies called Core Complex Dies (CCDs), each holding up to eight CPU cores, and pairs them with a separate I/O die that handles memory channels and PCIe lanes. If one CCD has a defect, AMD discards or downgrades only that small die, not an entire large processor's worth of silicon (AMD, "Zen 2 and Chiplet Architecture," Hot Chips 31 symposium, 2019).

Splitting the design this way has a second, related benefit that goes beyond yield alone: it lets each functional block use whichever manufacturing process actually suits its job. The I/O die, which handles analog circuitry and memory interfaces, does not benefit much from shrinking onto the newest, densest transistor node, because analog and interface circuits do not scale the same way digital logic does. AMD builds its I/O die on an older, cheaper process (12 nanometers in early EPYC generations) while the CPU compute dies use a newer, denser node such as TSMC's 7-nanometer or 5-nanometer processes. That mix-and-match approach, sometimes called "heterogeneous integration," means AMD is not forced to pay leading-edge wafer prices for circuitry that gets no real benefit from leading-edge transistors.

How the dies talk to each other

The hard part of a chiplet design is not cutting a chip into pieces. It is making those pieces behave, from the perspective of software, like one continuous chip. If the interconnect linking the dies is too slow, too high-latency, or too power-hungry, the yield savings get eaten alive by a performance penalty, and the whole exercise backfires.

AMD's answer is Infinity Fabric, a proprietary on-package and off-package interconnect that links CCDs to the central I/O die with enough aggregate bandwidth that an operating system has no visibility into the fact that the CPU is physically split across several pieces of silicon. Infinity Fabric operates at the physical layer as a coherent fabric, meaning it keeps cache and memory data consistent across dies the same way a single monolithic die's internal bus would, just with more distance for the signal to travel (AMD technical documentation, "AMD Infinity Architecture").

Intel's competing approach takes a different physical form. Foveros is Intel's 3D die-stacking technology, which places one active die directly on top of another and connects them vertically through-silicon vias, tiny conductive channels drilled through the silicon itself. EMIB (Embedded Multi-die Interconnect Bridge) is Intel's side-by-side approach, which embeds a small silicon bridge chip into the package substrate to connect two dies sitting next to each other at very high bandwidth over a very short distance (Intel, "Foveros and EMIB Packaging Technologies," Intel Newsroom technical briefings). Both approaches aim at the same goal as Infinity Fabric: keep the electrical distance between dies as short as possible, because distance is what turns a die-to-die link into a latency and power cost.

The tradeoff is real and worth stating plainly: a true monolithic chip has zero die-to-die latency, because every signal stays on one continuous, uninterrupted piece of silicon. A chiplet design always pays some penalty for crossing the physical seam between dies, even with the fastest interconnect available. Chip architects manage that penalty by using wide, short, extremely high-bandwidth physical links, and by deliberately keeping tightly coupled work, such as cores that frequently share the same cache line, on the same die whenever the workload allows it.

Why interconnect bandwidth matters more than interconnect existence

A slow interconnect can erase all of the yield savings a chiplet design was built to capture. If moving data between dies takes long enough to stall a CPU core waiting on a cache line, the chip loses real-world performance even though it is, on paper, cheaper to manufacture. This is why AMD, Intel, and the broader industry have invested heavily in standardizing die-to-die interconnect bandwidth and signaling, rather than treating it as an afterthought.

The UCIe standardization effort

UCIe (Universal Chiplet Interconnect Express) — an open industry standard for the physical and protocol layers that let chiplets from different vendors and different manufacturing processes talk to each other reliably. The UCIe Consortium was formally incorporated in 2022, with founding and board members including AMD, Intel, Arm, Qualcomm, Samsung, TSMC, Google Cloud, Meta, Microsoft, and Advanced Semiconductor Engineering (ASE), later joined by Alibaba and Nvidia as elected board members (UCIe Consortium, incorporation announcement, August 2022). Before UCIe, a chiplet built by one company generally could not be mixed and matched with a chiplet from a different vendor, because each company used its own proprietary die-to-die signaling scheme. UCIe aims to make chiplets interoperable the way USB made peripherals interoperable, letting a system integrator combine dies from multiple vendors and multiple process nodes inside one package.

Why this matters beyond desktop CPUs

Chiplet-style "tile" designs now extend well past AMD's original CCD approach, and the pattern shows up across nearly every high-performance chip category shipping today. Intel's Meteor Lake laptop processors, launched in December 2023, split compute, graphics, and I/O functions onto separate tiles built on different process nodes from different foundries, all stitched together with Foveros packaging (Intel, Meteor Lake architecture briefing, 2023). Apple's M1 Ultra chip, introduced in March 2022, fuses two complete M1 Max dies together using a proprietary die-to-die interconnect Apple calls UltraFusion, effectively doubling the chip's core count and memory bandwidth while presenting software with the abstraction of one single, unified processor (Apple, M1 Ultra product announcement, 2022).

The result of this shift is that processor "size," in the sense of total transistor count and total compute capability, is no longer bound by the largest single die a fab can reliably print at acceptable yield. A company can keep adding dies to a package, the way AMD does with its largest EPYC server chips, which use as many as 12 CCDs paired with a central I/O die, to scale total core counts far beyond what any single monolithic die could achieve without yield collapsing to an uneconomical level. This is also central to why modern high-end GPUs, which are among the largest and most expensive dies in the industry, are increasingly moving toward multi-die packages as well: the reticle limit and yield economics apply just as harshly to a GPU die as to a CPU die, if not more so, given how large GPU dies already are.

There is a broader economic story here too. Splitting a chip into chiplets also changes how a company can respond to demand and defects across a product line. A defective CCD that fails at the highest clock speed bin does not have to be scrapped entirely; it can be sold into a lower-clocked, lower-price product tier, a practice called "binning" that chipmakers have used for decades but that chiplets make more granular, because a defect in one small die does not necessarily disqualify the rest of the package.

Where chiplets fall short and what they cost

None of this comes free, and a fair account of chiplet design has to include the real costs, not just the yield upside. Packaging a multi-die chip is itself a manufacturing step with its own defect rate, called assembly yield, separate from the wafer-level yield of each individual die. If the process of physically bonding dies together in one package introduces its own failure rate, some of the yield gained at the die level gets given back at the packaging level.

Interconnect power is a second real cost. Moving a signal across a physical die-to-die interconnect consumes more energy per bit than moving the same signal across an internal on-die wire, because the interconnect has to drive a longer, more electrically noisy path, often through the package substrate itself. On a power-constrained device, such as a laptop or a phone, that overhead is not trivial, and it is part of why chiplet adoption has moved into mobile and laptop chips more slowly than into server and desktop parts, where power budgets are more forgiving.

Thermal density is a third consideration. Stacking dies vertically, as Intel's Foveros does, concentrates heat-generating logic into a smaller physical footprint, which can make heat removal harder rather than easier compared with spreading the same transistor count across a single flat die. Engineers have to design the package's thermal interface and, in some cases, add through-silicon cooling structures to manage this, which adds cost and design complexity on top of the interconnect problem.

Monolithic versus chiplet design, side by side

Everything covered so far, yield probability, interconnect penalties, packaging cost, boils down to a single economic comparison chipmakers run before committing a design to either approach. The table below summarizes how the two strategies stack up on the factors that actually decide which one a company picks for a given product.

Factor	Monolithic die	Chiplet design
Effect of die size on yield	Yield falls off sharply as die area grows, following Murphy's yield model; a single large die near the reticle limit can see yields drop to roughly 60% or lower at typical leading-edge defect densities	Each individual chiplet stays small, so yield per die remains high, often 90%+, even though multiple chiplets must be assembled into one package
Cost impact of a single defect	A defect anywhere on a large die scraps the entire processor's worth of silicon	A defect scraps only the small chiplet it occurred on; the rest of the package is unaffected and can often still be sold in a lower-tier product
Process-node flexibility	The entire die must be manufactured on one process node, even for circuitry, like analog I/O, that gains little from the newest, most expensive node	Different chiplets can use different, node-appropriate processes; e.g., AMD builds I/O dies on an older, cheaper node while compute dies use the newest node
Interconnect/latency cost	Zero; all circuitry shares one continuous piece of silicon with no die-to-die signal crossing	Real but managed; die-to-die links like Infinity Fabric, Foveros, or EMIB add latency and power that architects must design around
Scalability of core/transistor count	Capped by the reticle limit and by yield economics; pushing past it means yields collapse to an uneconomical level	Can scale well past what any single monolithic die could yield economically, by adding more small dies to the same package
Assembly/packaging risk	None beyond standard single-die packaging	Additional "assembly yield" risk from bonding multiple dies together, a separate failure mode on top of each die's own wafer-level yield

Chiplets trade a simpler, single-die manufacturing process for higher aggregate yield and node flexibility, at the cost of interconnect engineering and a second, packaging-level yield risk that monolithic dies never have to manage.

This comparison also explains why the crossover point tends to sit at the high end of the market rather than the low end. A small, simple die is already comfortably inside the yield curve's flat, high-yield region, so there's little economic pressure to split it further. A large, complex die sitting near or above the reticle limit is exactly where Murphy's yield model predicts the steepest yield losses, which is exactly where chiplets deliver the largest economic benefit relative to their added interconnect and packaging costs.

What people get wrong about chiplets

A common misconception is that chiplets are simply "smaller chips glued together" with no real engineering cost, as if splitting a die were a free lunch that every chipmaker was simply too slow to notice. In practice, the interconnect, the packaging, the power delivery across die boundaries, and the assembly yield are themselves genuinely difficult engineering problems, and a poorly designed chiplet link can erase the yield benefit entirely by introducing latency or power overhead that hurts real-world performance more than the manufacturing savings help the bottom line.

Another mistake is assuming every chip benefits from a chiplet approach. For small, simple chips, such as microcontrollers or low-end mobile system-on-chips, the die is already tiny enough that yield is not a major economic problem in the first place. Splitting a chip that is already small into even smaller pieces adds packaging complexity and interconnect cost without a meaningful yield payoff, since Murphy's yield model shows the benefit of splitting scales with how large and how likely-to-fail the original monolithic die would have been. Chiplets earn their keep specifically at the large, complex end of chip design, in high-core-count server processors, high-end desktop CPUs, and large GPUs, where the alternative monolithic die would sit near or above the reticle limit and suffer accordingly at the wafer.

A third, more subtle misconception is treating chiplets as a single, uniform technology. AMD's side-by-side Infinity Fabric approach, Intel's vertically stacked Foveros approach, and Apple's fused UltraFusion approach are meaningfully different engineering solutions to the same underlying yield problem, each with its own latency, power, and thermal tradeoffs. The industry has not converged on one physical implementation, even as it converges toward a shared logical standard through efforts like UCIe.

What comes next for chiplet design

The direction of travel across the industry points toward chiplets becoming the default approach for any processor large enough to sit near the reticle limit, rather than a niche technique reserved for AMD's server line. As UCIe matures past its initial specification releases, the promise of mixing dies from different vendors and different foundries inside one package moves from a theoretical goal toward something system integrators can actually design around, which could open the door to smaller companies building custom chips out of licensed, off-the-shelf chiplets rather than designing an entire monolithic die from scratch.

That shift would mirror what happened decades earlier in printed circuit board design, when manufacturers stopped designing every component from raw components and started assembling systems out of standardized, interchangeable parts. Whether chiplet interoperability reaches that level of maturity depends heavily on whether UCIe's member companies keep converging on shared physical and protocol layers rather than defaulting back to proprietary interconnects for competitive advantage.

The takeaway

Chiplets exist because manufacturing physics punishes large dies more than proportionally to their size, a relationship formalized in yield models like Murphy's model and confirmed repeatedly in real foundry data. By splitting a processor into smaller pieces, building each piece on the process node best suited to its job, and connecting them with a fast, low-latency interconnect such as AMD's Infinity Fabric or Intel's Foveros and EMIB, designers sidestep the yield cliff while still scaling core counts upward. It is an economics-driven shift as much as an engineering one, reinforced by an industry-wide standardization effort in UCIe, and it explains why modern high-end CPUs and GPUs from AMD, Intel, Apple, and Nvidia increasingly look like several chips wearing one processor's name.

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FAQ

Q: What is a chiplet, in simple terms?

A chiplet is a small, self-contained piece of silicon that handles part of a processor's job, like a cluster of CPU cores or an I/O controller, and is packaged together with other chiplets to form one complete chip, rather than etching everything onto a single large die.

Q: Why don't all chips use chiplets?

Small, simple chips already have high manufacturing yield at their size, so splitting them into chiplets adds packaging cost and interconnect power and latency without a meaningful yield benefit. Chiplets pay off mainly on large, complex chips like server CPUs and GPUs, where the monolithic alternative would sit near the reticle limit and suffer a steep yield penalty.

Q: Does splitting a chip into chiplets slow it down?

Signals crossing between separate dies take longer and cost more power than signals staying on one continuous die, so chip designers keep tightly coupled work on the same die and use wide, high-bandwidth interconnects like AMD's Infinity Fabric or Intel's EMIB to minimize the penalty. The gap never fully closes, but it is small enough that the yield savings usually outweigh it at large die sizes.

Q: Who uses chiplet designs today?

AMD popularized the modern approach with its Zen 2 EPYC and Ryzen processors starting in 2019. Intel uses Foveros die-stacking and EMIB bridging in chips like Meteor Lake, and Apple fuses dies together with its proprietary UltraFusion interconnect in the M1 Ultra and M2 Ultra chips.

Q: What is UCIe and why does it matter?

UCIe, or Universal Chiplet Interconnect Express, is an open industry standard for chiplet-to-chiplet interconnects, incorporated in 2022 by founding members including AMD, Intel, Arm, Qualcomm, Samsung, and TSMC. It aims to let chiplets from different vendors and manufacturing processes work together in one package, rather than each company relying on its own proprietary interconnect.