How Semiconductors Are Made

A modern smartphone processor packs more than 15 billion transistors onto a sliver of silicon smaller than a fingernail, and each one starts life as ordinary sand. Turning that sand into a working chip takes roughly three months, hundreds of individual processing steps, and machines so precise that a single dust particle can ruin a $20,000 wafer. This is the step-by-step story of how it actually happens, from melted quartz to the processor inside the device you're reading this on.

Why chipmaking is the hardest manufacturing process humans have ever industrialized

Building a semiconductor is not like building a car or a phone case. A modern logic chip requires patterning features smaller than 10 nanometers wide, which is around 40 times smaller than a coronavirus particle and roughly 10,000 times thinner than a human hair. At that scale, ordinary manufacturing tolerances stop applying, because a misalignment of even a few atoms can break an entire circuit.

The industry solves this with an approach called photolithography — using light to project a circuit pattern onto a light-sensitive chemical layer on a silicon wafer, the same basic idea as developing a photograph, except the "photo" is a blueprint for wires and transistors, and the exposure has to be repeated dozens of times with nanometer-level accuracy on the same piece of silicon. A single flagship chip can require more than 80 individual lithography passes stacked precisely on top of one another (Intel Newsroom, 2021).

The cost reflects the difficulty. A leading-edge fab capable of manufacturing 3-nanometer chips costs an estimated $15 billion to $20 billion to build (PatentPC, 2025), and a single extreme ultraviolet lithography machine from the Dutch company ASML — the only company in the world that makes them — costs $183 million to $220 million per unit, with the newest high-numerical-aperture models running $350 million to $400 million each (FourWeekMBA, 2026; MIT Technology Review, 2026). That is why only three companies on Earth currently manufacture chips at the most advanced process nodes: TSMC in Taiwan, Samsung in South Korea, and Intel in the United States.

A single ASML EUV lithography machine can cost more than an Airbus A350 jet, and it takes roughly 40 cargo planes and 20 trucks just to ship one to a customer's fab.

Where a chip actually begins: growing a perfect crystal of silicon

Every chip starts as silicon dioxide, which is the chemical name for the quartz found in ordinary sand. Manufacturers heat it with carbon in a furnace at around 2,000°C to strip away the oxygen, leaving metallurgical-grade silicon that is roughly 98 percent pure. That's nowhere near pure enough. Through a further chemical purification process, the silicon is refined to "electronic grade" purity of 99.9999999 percent, meaning fewer than one impurity atom for every billion silicon atoms (WaferPro).

That ultra-pure silicon is then melted and turned into a single, flawless crystal using the Czochralski process, named after the Polish chemist who discovered it in 1916. A small seed crystal is dipped into a crucible of molten silicon held at 1,414°C and slowly pulled upward while both the seed and the crucible rotate in opposite directions. As it rises, silicon atoms attach themselves to the seed in perfect crystalline alignment, growing a cylindrical ingot that can reach 300 millimeters (about 12 inches) in diameter and more than a meter long (UniversityWafer; MKS Instruments).

Think of it like dipping a stick into honey and slowly twirling it out, except instead of a messy drip you get a geometrically perfect crystal with every atom locked into the same repeating lattice, because any misaligned atom becomes a defect that can short-circuit a transistor later.

Why does silicon need to be a single crystal instead of just pure metal?

Silicon's usefulness comes from its atomic lattice, the repeating 3D grid pattern its atoms naturally form. Electrons move predictably through a single, defect-free lattice, which is what lets engineers control electrical current with precision. A polycrystalline or impure structure has boundaries and defects that scatter electrons randomly, making reliable transistor switching impossible.

Once the ingot cools, it's sliced into wafers roughly 0.75 millimeters thick using a wire saw strung with diamond-coated wire, then polished with a chemical slurry until the surface is flat to within a few atoms — smooth enough that a wafer the size of a dinner plate would have peaks and valleys no bigger than a few nanometers if scaled up to the size of a football field.

The fab floor: how a blank wafer becomes a working circuit

A raw silicon wafer is just a mirror-flat disc of pure crystal. It has to acquire electrical properties in specific patterns, thousands of times, layer by layer, before it becomes a chip. This happens inside a cleanroom, a manufacturing space engineered to keep airborne particle counts thousands of times lower than a hospital operating room, because a single speck of dust bigger than a few tens of nanometers can destroy a transistor.

Four core process categories repeat over and over, sometimes hundreds of times, to build up a chip's structure.

Process step	What it does	Typical method	Why it matters
Photolithography	Projects the circuit pattern onto a light-sensitive coating	EUV (13.5nm light) or deep UV lasers through a patterned mask	Defines where every transistor, wire, and gate will sit
Etching	Removes unwanted material to carve the pattern into the wafer	Plasma (dry etch) or chemical baths (wet etch)	Turns the 2D light pattern into a physical 3D structure
Doping	Adds impurity atoms to change silicon's electrical behavior	Ion implantation — firing charged atoms into the wafer	Creates the positive and negative regions a transistor needs to switch on and off
Deposition	Adds thin layers of new material onto the wafer	Chemical vapor deposition or physical vapor deposition	Builds insulating layers and metal wiring between transistor layers

Each finished transistor layer requires all four steps in sequence, and a modern chip stacks dozens of layers on top of each other.

How does EUV lithography actually create such tiny features?

Extreme ultraviolet (EUV) lithography uses light with a wavelength of 13.5 nanometers, generated by blasting molten tin droplets with a high-power laser 50,000 times per second to create a plasma that emits EUV radiation. That light is bounced off a series of atomically smooth mirrors, patterned by a mask, and focused onto the wafer to print features far smaller than visible-light lithography ever could (ASML; MIT Technology Review, 2026). It replaced older deep ultraviolet techniques starting around 2019 because circuit features had shrunk past what longer wavelengths could resolve.

After each lithography and etch cycle, the wafer goes through ion implantation, where a particle accelerator fires dopant atoms like boron or phosphorus into precise regions of the silicon at controlled energies and depths. Boron creates "p-type" silicon with a shortage of free electrons; phosphorus creates "n-type" silicon with an excess. Placing these regions next to each other is literally what makes a transistor — the junction between them is the switch that turns a "1" into a "0" and back again.

From wafer to finished chip: testing, cutting, and packaging

A finished 300-millimeter wafer holds hundreds of identical chip patterns, called dies, repeated in a grid. Before anything is cut apart, every single die is electrically tested in place — a process called wafer sort or electrical die sort — using a probe card that touches thousands of contact points simultaneously to confirm each die actually functions.

This step matters more than it sounds like it should, because yield, the percentage of dies on a wafer that work correctly, is the single biggest cost driver in chipmaking. At the most advanced nodes, a fab might start out with yields well under 70 percent, and every improvement in yield directly increases how many sellable chips come out of a wafer that costs tens of thousands of dollars to process regardless of how many dies pass. This is closely related to the economics discussed in why chiplets are changing processor design — splitting one large processor into several smaller chiplets means a single defect only ruins a small chiplet instead of an entire monolithic die, which is one of the biggest reasons the industry has shifted toward chiplet-based designs.

Once tested, the wafer is sliced apart with a diamond saw or laser, separating the individual dies. The good dies move on to packaging, where they're mounted onto a substrate, wired to external pins or solder balls, and sealed to protect them from moisture, dust, and physical damage. Modern high-end packaging can also stack multiple dies vertically or place several chiplets side by side on a shared interposer, connecting them with interconnect technologies like TSMC's CoWoS or Intel's Foveros. Packaging used to be an afterthought in chip design; today it's a competitive battleground in its own right, because it's one of the few remaining ways to keep boosting performance as transistor shrinking slows down.

Inside the back end: how packaging and final test actually work

The steps described above, growing the crystal, patterning it, and cutting it into dies, are collectively called the "front end" of chipmaking. Everything that happens after a good die is identified is called the "back end," and it gets far less attention even though it is the final gate standing between a functioning die and a chip that can survive being soldered into a real device (Rapidus Corporation).

The first decision is how to electrically connect the bare die to the outside world. The oldest and still widely used method is wire bonding, where extremely thin gold or copper wires are welded between contact pads on the die and matching pads on the package substrate, one connection at a time. It's reliable and cheap, but every wire adds a small amount of electrical resistance and delay, which becomes a real problem once a chip needs thousands of connections switching billions of times a second.

High-performance chips instead use flip-chip packaging. Rather than wiring pads around the die's edge, the entire face of the die is covered with tiny solder bumps, the wafer is diced, and each die is flipped upside down and bonded directly onto the substrate so every bump makes contact at once. A resin, called underfill, is injected into the remaining gap to lock the connections in place mechanically, and the whole assembly is sealed with molded resin (ASE; Rapidus Corporation). Because connections form across the entire face of the chip rather than just around its perimeter, flip-chip packaging supports far more connections, lower resistance, and higher speeds than wire bonding, which is why it dominates in CPUs, GPUs, and other high-performance logic.

For chips that plug into a circuit board rather than sitting inside another package, manufacturers commonly finish with ball grid array (BGA) packaging, where the underside of the finished package is studded with a grid of small solder balls instead of pins. BGA packages handle the higher power and heat loads of demanding chips better than older pin-based designs, which is part of why they became standard for everything from smartphone processors to server chips (ELE Times; ASE).

What is burn-in testing and why does every chip go through it?

A finished, packaged chip still isn't shipped straight to a customer. It goes through a sequence of final tests, and the most demanding of these is burn-in, where chips are run at elevated voltage and temperature for an extended period to force any latent defect to fail early rather than after the chip is already inside a customer's product. Manufacturers run a preliminary test before burn-in to screen out chips that are so obviously defective they would risk damaging the expensive burn-in equipment itself, then run burn-in, then run a second final test afterward to sort the survivors, and finally mark, inspect, and package the units that pass for shipment (Rapidus Corporation).

This matters because semiconductor failures cluster into a well-known "bathtub curve": a chip with a hidden manufacturing flaw is statistically most likely to fail either very early in its life or very late, and burn-in exists specifically to force early failures to happen on the test floor instead of inside a customer's laptop, car, or data center. For chips headed into safety-critical uses, such as automotive or aerospace electronics, burn-in and final test can add a significant share of total manufacturing time on top of the front-end fabrication process already described.

The global foundry landscape: who actually makes the world's chips

Almost no company designs and manufactures its own most advanced chips anymore. Instead, the industry has split into "fabless" companies that design chips — Apple, Nvidia, AMD, Qualcomm — and foundries that manufacture them under contract. Three companies currently operate at or near the industry's most advanced process nodes.

TSMC (Taiwan Semiconductor Manufacturing Company) is the world's largest contract chipmaker and manufactures the majority of the world's most advanced logic chips, including for Apple and Nvidia. Samsung Foundry runs a competing advanced-node business out of South Korea and supplies chips for its own Galaxy devices as well as external customers. Intel, historically an integrated device manufacturer that only made its own chips, has been building out Intel Foundry as a contract manufacturing business for outside customers as part of its turnaround strategy.

This concentration is a direct consequence of the costs described earlier. When a single EUV machine costs hundreds of millions of dollars and a leading-edge fab costs tens of billions to build, only a handful of companies in the world can afford to compete at the cutting edge, and even TSMC has reportedly delayed adopting ASML's newest $410 million high-numerical-aperture EUV systems specifically because of the cost, choosing instead to extend its current low-NA EUV tools using more complex multi-patterning techniques (Tom's Hardware, 2026; AnySilicon).

Why does one company, ASML, control the entire EUV lithography market?

ASML is the sole global supplier of EUV lithography machines because building one requires integrating technology so specialized — atomically precise mirrors from Zeiss, high-power tin-plasma laser sources, vacuum systems capable of holding a near-perfect vacuum around moving optics — that no competitor has successfully replicated the full supply chain. Decades of R&D and patents built a moat few companies can cross.

What people get wrong about how chips are made

A common misconception is that "smaller nanometer number" is a literal physical measurement of transistor size. It hasn't been for years. Node names like "7nm" or "3nm" are now marketing labels tied loosely to a generation of manufacturing technology rather than the literal gate length of a transistor, which is why a "5nm" chip from one foundry isn't directly comparable in density or performance to a "5nm" chip from a competitor. Analysts typically compare fabs using transistor density per square millimeter instead, which is a more consistent measure.

Another frequent mistake is assuming that Moore's Law — the observation that transistor counts on a chip roughly double every two years — has simply stopped. It has slowed and become far more expensive to sustain, which is part of why the industry increasingly relies on chiplets, 3D stacking, and packaging innovations rather than pure transistor shrinking to keep performance climbing. It's less a dead trend than a trend that changed its main lever.

People also underestimate how much of a finished chip's cost comes from testing and packaging rather than the wafer fabrication itself. Advanced packaging, final test, and yield losses can account for a substantial share of total manufacturing cost on the most complex chips, particularly ones that stack multiple chiplets or use high-bandwidth memory, which is why "final assembly" is no longer treated as a cheap, low-skill step tacked onto the end of the process.

Finally, many assume any company with enough money could build a competitive fab. In practice, the knowledge required — process recipes refined over years, defect-control expertise, supplier relationships for equipment with years-long order backlogs — is at least as hard to replicate as the capital itself. That's a core reason why the field this article covers connects to broader questions the site explores in EUV lithography explained, where the machine at the center of modern chipmaking gets a deeper technical breakdown.

The takeaway

A semiconductor chip is the product of one of the most precise, capital-intensive supply chains humans have ever built, starting from ordinary sand and ending with a circuit whose smallest features are measured in atoms. The process runs through crystal growth, repeated lithography-etch-dope-deposit cycles, testing, and increasingly sophisticated packaging, and each stage compounds the difficulty and cost of the last. Because only a few companies worldwide can afford the equipment and expertise required at the leading edge, the modern chip industry is as much a story about geopolitics and supply-chain concentration as it is about physics — and that concentration is unlikely to loosen anytime soon, given how far ahead the leaders already are.

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Read next:

• Why Chiplets Are Changing Processor Design
• EUV Lithography Explained
• Quantum Computing Explained Simply

FAQ

Q: What raw material are semiconductors made from? Semiconductors are made from silicon refined from silicon dioxide, the compound found in ordinary quartz sand. The sand is purified to 99.9999999 percent purity, then grown into a single, defect-free crystal ingot using the Czochralski process before being sliced into wafers (WaferPro).

Q: How long does it take to manufacture a single chip? A modern logic chip typically takes about 11 to 14 weeks from a raw wafer to a finished, tested die, because each of the dozens of transistor layers requires its own cycle of lithography, etching, doping, and deposition, all performed with nanometer-level precision.

Q: Why is EUV lithography necessary for advanced chips? Older deep ultraviolet lithography uses light wavelengths too long to reliably print features below about 30 to 40 nanometers. EUV lithography uses 13.5-nanometer light, generated from laser-vaporized tin plasma, to print far smaller features, which is what enables today's 3-nanometer and 2-nanometer process nodes (ASML; MIT Technology Review, 2026).

Q: Why do only a few companies make the most advanced chips? Leading-edge fabs cost an estimated $15 billion to $20 billion to build, and the EUV lithography machines inside them cost $183 million to more than $400 million each from ASML, the sole global supplier. That capital barrier, combined with decades of accumulated process expertise, limits the most advanced manufacturing to TSMC, Samsung, and Intel (PatentPC, 2025; FourWeekMBA, 2026).

Q: What does "doping" mean in chip manufacturing? Doping is the process of implanting impurity atoms like boron or phosphorus into precise regions of a silicon wafer to change how it conducts electricity. Boron creates electron-deficient "p-type" silicon and phosphorus creates electron-rich "n-type" silicon; the junction between these regions forms the basic switching mechanism of a transistor.

Q: What is yield, and why does it matter so much in chip manufacturing? Yield is the percentage of dies on a wafer that pass electrical testing and function correctly. Because a wafer costs the same to process regardless of how many dies work, yield directly determines the cost per usable chip, which is why foundries invest heavily in defect control and why designs like chiplets exist partly to limit how much a single defect can waste.