EUV Lithography Explained: The Machine Behind Advanced Chips

Every advanced chip in a modern smartphone or AI data center was printed by light so specific that only one company on Earth knows how to generate it reliably at industrial scale. Extreme ultraviolet (EUV) lithography uses 13.5-nanometer light, produced by vaporizing microscopic droplets of molten tin with a laser, to project circuit patterns onto silicon wafers. This guide explains why that light is so hard to make, how the machine that makes it works step by step, and why a single tool can cost more than $200 million.

What EUV lithography actually is

Lithography — the process of transferring a circuit pattern onto a silicon wafer using light and light-sensitive chemicals — is the step that defines how small a chip's transistors can be. For decades, chipmakers used deep ultraviolet (DUV) light at 193 nanometers, a wavelength borrowed from older excimer lasers, and stretched that technology further than physicists thought possible through tricks like immersion lithography and multiple patterning, where a single layer is exposed several times to fake a smaller feature.

By the mid-2010s those tricks ran out of headroom. Multi-patterning at 193nm required so many extra exposure and etch steps that chips became slower and more expensive to make, and yield — the percentage of working chips per wafer — kept dropping as complexity rose. The industry needed a fundamentally shorter wavelength, and 13.5 nanometers, sitting in the extreme ultraviolet band, was the target physicists had eyed since the 1980s.

The obstacle was never picking the wavelength. It was generating it. EUV light at 13.5nm is absorbed by essentially everything, including air, glass lenses, and standard mirrors, which means the entire optical path from light source to wafer has to run in a near-vacuum and use specially engineered mirrors instead of lenses. ASML, the Dutch company that holds a global monopoly on EUV scanners, spent roughly 17 years and an estimated $9 billion in R&D, much of it with US Department of Energy national labs, before shipping the first production EUV system in 2017 (ASML technology overview).

To generate EUV light, ASML's machines heat vaporized tin plasma to nearly 220,000°C — about 40 times hotter than the surface of the sun — inside a chamber the size of a small car, thousands of times per second.

How the light is actually made

The mechanism starts with tin, not a laser directly. A generator fires roughly 25-micron droplets of molten tin, about half the width of a human hair, into a vacuum chamber at speeds around 70 meters per second (about 250 km/h, or 155 mph). A first, low-power laser pulse hits each droplet and flattens it into a pancake shape to maximize surface area. A fraction of a microsecond later, a second, far more powerful CO2 laser pulse strikes that flattened droplet and vaporizes it into a plasma hot enough to emit EUV light (Heise, 2024).

Think of it like flash photography for atoms: the first laser pulse is the "focus" step that shapes the target, and the second pulse is the flash that actually produces usable light — except the flash here converts tin into a plasma nearly as hot as a stellar interior, tens of thousands of times per second, inside a machine sitting on a factory floor. That plasma radiates light across many wavelengths, and a curved collector mirror captures only the useful 13.5nm slice and focuses it toward the lithography optics.

Because current production systems fire around 50,000 droplets per second, and each droplet only converts a fraction of its mass into usable EUV photons, the process is inherently inefficient. ASML has been raising output by increasing droplet frequency and adding extra pre-pulses: a 2026 upgrade path aims to roughly double droplet rate toward 100,000 per second and use three laser shots per droplet, two to shape it and one to ignite it, pushing source power from about 600 watts toward 1,000 watts (search-sourced ASML light source roadmap coverage, 2026). More source power directly means more wafers processed per hour, which is the metric fabs actually pay for.

Why can't you just use a regular laser at 13.5nm directly?

No material can act as an efficient EUV laser gain medium at that wavelength, and EUV photons are absorbed almost instantly by any transparent lens. Generating the light from a hot plasma and then reflecting it with specialized mirrors is currently the only method that produces enough usable power for industrial manufacturing.

Inside the machine: mirrors, vacuum, and a reticle

Once the 13.5nm light is collected, it cannot pass through a normal glass lens the way visible light does in a camera lens, because EUV photons are absorbed by essentially every transparent material available. Instead, ASML's scanners route the light through a series of ultra-precise curved mirrors, made by the German optics company Zeiss, coated with alternating molybdenum and silicon layers only a few atoms thick that are tuned to reflect 13.5nm light through constructive interference rather than transmit it.

Each mirror in the optical path absorbs some of the light, so a production EUV system may use ten or more mirrors between the source and the wafer, and each mirror surface has to be polished to a flatness measured in picometers — a level of precision often compared to scaling a smooth error the size of a single atom across a surface the diameter of a small country. This is one of the two hardest engineering problems in the whole machine, alongside the light source itself.

The pattern to be printed lives on a reticle (also called a photomask) — a reflective glass plate coated with a patterned absorber layer that blocks EUV light in some areas and reflects it in others, essentially a stencil for the chip's circuit layer. The reflected, patterned light passes through a final set of projection mirrors that shrink the image by a factor of four, then exposes a light-sensitive chemical coating called photoresist on the silicon wafer below. Wherever EUV light hits the photoresist, a chemical reaction occurs that later allows those exact regions to be etched away or left behind, transferring the circuit pattern permanently into the silicon.

The entire optical path, source to wafer, runs inside a vacuum, because EUV light is absorbed by air itself. Any contamination — a stray tin droplet residue, a dust particle, a hydrocarbon molecule — can degrade the mirrors or ruin a wafer worth thousands of dollars, which is why EUV fabs run some of the cleanest manufacturing environments ever built, with fewer particles per cubic meter than a hospital operating room.

Why so few companies can afford or operate it

A single production EUV scanner, ASML's TWINSCAN NXE series, costs roughly $150 to $200 million, and the newer High-NA generation, the TWINSCAN EXE:5000 series with a numerical aperture of 0.55 versus 0.33 in prior systems, costs substantially more (ASML product page). That higher numerical aperture — a measure of how much light angle the optics can capture and therefore how fine a feature they can resolve — lets High-NA machines print roughly 1.7 times smaller features in a single exposure than the previous generation, translating to about 2.9 times higher transistor density (Tom's Hardware, 2024).

Cost is only the entry fee. Operating an EUV fab also requires a facility built around the machine: vibration isolation so sensitive that nearby road traffic can be a design constraint, ultra-clean air handling, and a supply chain of specialized technicians who can service optics measured in picometers. That combination of capital cost and process expertise is why, as of 2026, only three companies run EUV in high-volume production: TSMC, Samsung, and Intel. TSMC alone reportedly operates a large share of the world's installed EUV scanner fleet, which is one reason a small area of Taiwan produces such an outsized share of the world's advanced-node chips — a dependency explored in more depth in why semiconductors are so hard to make.

It is worth being precise about the ownership question: ASML is the only company that manufactures and sells EUV lithography systems. Chipmakers buy the machines but do not build their own competing versions, because the mirror technology, the plasma light source, and the metrology are each individually near-monopolies held by ASML and its supplier network.

Why does TSMC dominate EUV manufacturing more than Intel or Samsung?

TSMC adopted EUV earlier and at greater scale for its foundry customers, including Apple and Nvidia, giving it more production experience and yield data per node transition. TSMC has also been more selective about which EUV generation to adopt — for example, delaying High-NA EUV adoption toward 2029 on cost grounds while Intel installed the first commercial High-NA tool in 2024 (TrendForce, 2026).

From Moore's Law crisis to AI chip supply chain

EUV exists because Moore's Law — the observation, credited to Intel co-founder Gordon Moore in 1965, that the number of transistors on a chip roughly doubles every two years — was on track to stall in the mid-2010s without a shorter lithography wavelength. Multi-patterned 193nm DUV could not economically keep shrinking transistor features below about 10 nanometers, and each added patterning step increased cost, cycle time, and defect risk.

EUV's arrival in production around 2019, first used commercially by Samsung and then scaled by TSMC for what became its 7-nanometer-plus and 5-nanometer nodes, let the industry return to single-exposure patterning for the tightest layers, cutting process steps and improving yield even as feature sizes kept shrinking. That single change is arguably the reason phones, laptops, and AI accelerators kept getting faster and more power-efficient on the same rough timeline the industry had promised for 60 years.

The connection to today's AI boom is direct rather than incidental. Training and running large AI models depends on GPUs and AI accelerators built at the same advanced nodes EUV enables — the parallel processing architecture behind that hardware is explained in how GPUs work and why AI needs them. Every generation of Nvidia or AMD AI chip that becomes more efficient per watt owes part of that gain to EUV letting transistors shrink further without abandoning single-pass lithography. When ASML's shipment schedule for EUV tools slips, it is not an obscure supply chain footnote, it is a leading indicator for how fast AI hardware capacity can grow.

Where EUV hits its limits

EUV is not a permanent solution, and it comes with real tradeoffs the industry openly acknowledges. Throughput remains a constraint: even with source power increases, an EUV scanner processes far fewer wafers per hour than a mature 193nm DUV tool doing simpler patterning, and fabs need dozens of scanners running in parallel to hit volume targets, each one representing hundreds of millions of dollars of capital.

Defectivity is another open problem. Because EUV photoresist layers are thinner and the exposure dose is lower than in DUV processes, EUV-patterned layers can be more sensitive to a class of random pattern-placement errors called stochastic defects, where photon-level randomness in a very thin resist causes unpredictable misprints at the nanometer scale. Chipmakers manage this with process controls and redundancy, but it has not been eliminated, and it is one reason some layers on a modern chip still use DUV multi-patterning where EUV would be technically possible but not yet more economical.

High-NA EUV, the next step already installed at Intel, faces its own new problem: the larger optics needed for 0.55 numerical aperture reduce the usable exposure field on the wafer roughly in half compared to standard EUV, which means chipmakers may need to "stitch" large chip designs across two exposures, adding complexity that partly offsets the resolution gain (Tom's Hardware, 2024). That tradeoff explains why TSMC, weighing cost against benefit, has been in no hurry to adopt High-NA on its current roadmap.

Generation	Wavelength	Numerical Aperture	Introduced	Typical Node Use
DUV immersion	193 nm	1.35	2007	Mature nodes, non-critical layers
EUV (Low-NA)	13.5 nm	0.33	2019 (volume)	7nm–3nm critical layers
High-NA EUV	13.5 nm	0.55	2024 (first install)	2nm and below, R&D through 2029+

Each lithography generation trades wavelength or optical aperture for finer resolution, at the cost of throughput, exposure field size, or capital expense.

Inside the tin droplet: an engineering problem measured in microseconds

The tin droplet generator is one of the least visible parts of an EUV scanner and one of the hardest to keep running reliably. Each droplet has to leave the generator, travel roughly 2 to 3 millimeters through vacuum, and arrive at the exact focal point of the laser at the exact moment the laser fires, thousands of times every second, with positioning accuracy on the order of micrometers. Miss that timing window and the laser pulse either hits nothing useful or vaporizes the droplet off-center, wasting energy and producing weaker, less usable EUV light.

Only a small fraction of each tin droplet's mass actually converts into the 13.5nm photons the scanner needs; the rest becomes debris, stray tin ions and neutral atoms that spray outward from the plasma in all directions. Left unmanaged, that debris would coat the expensive collector mirror sitting closest to the plasma within hours, degrading its reflectivity and shutting the machine down for cleaning. ASML's systems counter this with a combination of a low-pressure hydrogen buffer gas, which slows and scatters escaping tin ions before they reach the mirror, and a magnetic field that helps deflect charged debris away from the optical path, plus a periodic in-situ hydrogen-plasma cleaning cycle that etches accumulated tin off the collector without opening the machine to open air. Even with those measures, the mirror closest to the plasma source is effectively a wear part, one of the more direct reasons a fab budgets ongoing service contracts, not just the sticker price, when it buys a scanner.

The practical upshot of all that droplet engineering is uptime. A production fab cannot tolerate a machine that goes offline for cleaning every few days, since a single EUV scanner is often the pacing tool for an entire advanced-node production line. ASML has steadily pushed mean time between mirror-degrading events longer even as it has simultaneously pushed droplet frequency and laser power higher, which is why the source subsystem, not the projection optics, has historically been the slowest part of the roadmap to improve.

Why one country's export policy can slow the entire chip industry

Because ASML is the sole commercial source of EUV scanners, the Dutch government's export licensing decisions function as a global chokepoint independent of any single chipmaker's plans. Since 2019, the Netherlands has coordinated with the United States to restrict EUV system sales to China, and ASML has never shipped a production EUV tool there. That restriction has since crept toward the technology's less advanced predecessor: in April 2026, a bipartisan group of US lawmakers introduced the Multilateral Alignment of Technology Controls on Hardware (MATCH) Act, which would go further and ban exports of deep ultraviolet (DUV) immersion lithography systems to China too, along with servicing of DUV tools Chinese fabs already own (Motley Fool, April 2026; CNBC, April 2026).

The business impact is measurable rather than abstract: ASML expects China to account for roughly 20% of its total 2026 sales, down sharply from about 33% in 2025, as the restrictions tighten and backlogged Chinese orders clear (Motley Fool, 2026). For chipmakers outside China, the practical consequence of ASML's monopoly and the export-control regime is that lithography capacity gets allocated years in advance through direct negotiation with a single supplier, not purchased on an open market, which is one more reason TSMC, Samsung, and Intel treat their ASML relationships as strategic rather than transactional.

What people get wrong about EUV

The most common misconception is treating EUV as a single machine that "prints a chip." In reality, a modern chip requires dozens of separate lithography exposures across many layers, and EUV is typically reserved for only the most critical, smallest-feature layers, while DUV handles the rest. A chip is not "an EUV chip" so much as a chip with some EUV layers and many more conventional ones, a distinction covered in more depth in how semiconductors are made.

A second misconception is that EUV alone determines a chip's process node name, like "3nm" or "2nm." Those marketing names no longer correspond to a literal measured feature size; they are relative labels tied to a specific combination of lithography, transistor architecture (such as FinFET or gate-all-around designs), and materials, not a strict physical dimension. EUV enables the patterning precision those nodes need, but the node number itself is a commercial label, not a direct measurement of a transistor's smallest feature.

A third misconception is that EUV is a solved, static technology. ASML, Zeiss, and chipmakers are still actively engineering around throughput limits, stochastic defects, and the field-splitting tradeoff of High-NA optics. The version of EUV running in fabs in 2026 is meaningfully more capable than the systems first shipped in 2017, and the roadmap through Hyper-NA, an even more extreme optical design under research, suggests the technology is still evolving rather than finished.

The takeaway

EUV lithography solves a genuinely hard physics problem — generating and controlling light with a wavelength shorter than most matter can transmit — by vaporizing tin into a plasma nearly as hot as the sun's surface and steering the resulting light with mirrors flat to picometer precision. That capability, held almost entirely by one company, is what let chipmakers keep shrinking transistors past the point 193nm light could economically reach. The tradeoff is concentration: a technology this expensive and precise is only viable for a handful of companies, which is exactly why a small number of fabs, dominated by TSMC, now sit at the center of both the smartphone industry and the AI hardware boom.

---

Read next:

• /technology/how-semiconductors-are-made
• /technology/why-semiconductors-are-so-hard-to-make-inside-the-worlds-most-complex-manufacturing
• /technology/how-gpu-works-why-ai-needs-them

Frequently Asked Questions

Q: What wavelength of light does EUV lithography use, and why that number specifically? A: EUV lithography uses 13.5-nanometer light. That wavelength was chosen because it is short enough to pattern features far smaller than 193nm deep ultraviolet light allows, while still being a wavelength that specialized molybdenum-silicon mirrors can reflect efficiently.

Q: How is EUV light actually generated? A: A laser hits a droplet of molten tin twice: once to flatten it, and once with a stronger pulse to vaporize it into a plasma heated to roughly 220,000°C, which emits EUV light that a collector mirror focuses toward the lithography optics.

Q: Which companies can actually use EUV lithography in production? A: As of 2026, only TSMC, Samsung, and Intel operate EUV lithography at high-volume manufacturing scale, because a single scanner costs roughly $150–200 million and requires an entire cleanroom facility engineered around it.

Q: Is High-NA EUV the same as regular EUV? A: No. High-NA EUV uses a larger numerical aperture (0.55 versus 0.33) to resolve smaller features in a single exposure, but it also has a smaller usable exposure field on the wafer, which can require splitting large chip designs across two exposures.

Q: Why does EUV lithography matter for AI chips specifically? A: AI accelerators and GPUs depend on advanced process nodes that only EUV-capable fabs can produce at scale, so ASML's EUV tool shipment volume is a practical constraint on how quickly AI chip supply can expand.

Sources

• ASML — Light and lasers, lithography principles
• ASML — TWINSCAN EXE:5000 High-NA EUV product page
• Heise Online, "EUV Lithography: ASML will shoot tin droplets 300,000 times per second," 2024
• Tom's Hardware, "ASML's roadmap for chipmaking lithography tools examined," 2024
• TrendForce, "ASML's High-NA EUV for 2027-28," 2026
• New Electronics, "ASML announces breakthrough in EUV light source to boost chip output"
• The Motley Fool, "ASML Just Got Hit by a New China Export Threat," April 2026
• CNBC, "ASML shares fall after proposed U.S. export curbs target an already fragile China market," April 2026